Actel has unveiled its AX architecture, a new field-programmable gate array (FPGA) technology specifically developed to the meet the extreme-performance, high-capacity requirements of designers of leading-edge communication systems. According to Actel, AX was crafted with two key objectives in mind - to eliminate the performance bottlenecks and expensive work-arounds needed when pushing traditional FPGAs' performance; and to provide a scalable, logic-integration platform for future Actel product generations.
To address the performance bottleneck, Actel created an architecture that exceeds 500 MHz internal core performance - considered the industry's highest. To achieve its objectives, Actel integrated a number of new logic, routing, clock management, I/O and embedded features and functionality into the AX architecture.
The AX architecture features several key advancements: new high-speed, FIFOs for data buffering; an intelligent clock and clock-phase management system; and a scalable, tile-based, high-utilisation logic structure.
Embedded FIFO controller: The embedded FIFO control unit contains metastability immune control circuitry that supports high-performance communications design without using general device resources.
Fully fracturable SuperCluster: The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. As a result, the fully fracturable SuperCluster allows high logic module use.
Embedded 64-bit PerPin FIFO: The addition of an embedded 64-bit PerPin FIFO enables easy interfacing with off-chip resources on different clock domains.
Flexible clock structure: Available equally across the chip, the AX architecture includes eight PLLs and eight global clocks, which eliminates the need for clock floorplanning and eases design migration.
High-speed applications require a general-purpose FPGA architecture capable of handling high data rates coming on to the chip. With internal core performance over 500 MHz, more than 20% faster than industry-standard, the AX architecture is a suitable platform on which Actel can develop general-purpose and BridgeFPGA solutions for next-generation, high-speed communications applications.
Following the initial five Axcelerator family members, Actel plans to deliver additional derivatives over the next 18 months.
For more information: ASIC Design Services, 011 315 8316, [email protected]
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