Actel has announced qualification and availability of its single-chip, 'live-at-power-up' 72 000-gate RT54SX72S antifuse field-programmable gate array (FPGA). Actel also announced that the Defense Supply Center Columbus (DSSC) has approved the RT54SX72S FPGAs. This family is well suited to radiation-intensive applications, such as low-Earth orbiting satellites and deep space probes.
The RTSX-S family is the industry's first FPGA solution built on a foundation of hardened latches, which eliminates the need for software-based triple module redundancy (TMR) and thus maximises the total number of logic gates available to the designer according to the company. These devices offer total ionising dose (TID) performance in excess of 100 Krad; inherent single-event latchup (SEL) immunity; >63MeV-cm2/mg single-event upset (SEU) performance; and hot-swap compliant I/Os and cold-sparing capabilities.
The RT54SX72S has been fully characterised for the effects of TID, SEL and SEU. The RTSX-S family's SEU-hardened latch proved to be impervious to heavy ion upset far beyond the linear energy transfer (LET) threshold goal of >37MeV-cm2/mg; TID performance tested in excess of 100 Krad; and, consistent with all of Actel's radiation-hardened and radiation-tolerant devices, the RT54SX72S has tested immune to destructive heavy ion-induced SEL effects.
The RTSX-S family ranges in density from 32 000 to 72 000 typical gates (16 000 to 36 000 ASIC gates) and offers system performance in excess of 250 MHz. Traditional FPGAs, which do not use hardened latches, force the user to implement TMR using software or a large portion of the device's programmable logic. This process of majority voting, or redundancy, means that two-thirds of the density, or available logic, is consumed for redundancy and is not available for the user's design.
Software support for the RTSX-S family is provided by Actel's Libero integrated design environment.
For further information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected]
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