Today engineers are faced with numerous challenges at the moment of deciding which type of technology to apply for a specific task, especially when faced with misleading information about other solutions or technologies.
Consider motor control as an example. In an article recently published in Dataweek, I encountered the following statement made by a specialist at a prominent chip vendor: “The drawback of using an SoC-based design is that its lower processing performance and limited internal memory mean that it cannot meet the demands of applications which need advanced motor control.”
I have to say I completely and strongly disagree. It is not my intention to diminish or degrade other technologies. In fact, I believe there are different technologies from different silicon manufacturers that are very well suited for specific tasks. However, the above statement suggests the author is not very knowledgeable about the solutions that other vendors have to offer; quite frankly it is both misleading and a little insulting. To begin with, the first part of the statement, concerning the performance of an SoC-based design, is questionable and warrants closer scrutiny.
SoCs (systems-on-chip) like the SmartFusion2 devices from Microsemi, provide a very powerful and versatile platform for design, combining a hardwired microprocessor and an FPGA. I believe this SoC solution offers a significant advantage over a standalone micro-processor solution as it enables hardware/software co-processing, provides parallel processing and deterministic performance (in the FPGA) and has a high degree of flexibility (configurable and scalable).
Furthermore, the Microsemi motor control solution offers a complete set of IP (intellectual property) for motor control for fast, flexible, reliable and secure design of field-oriented control. In simple terms, this SoC device can execute a 6-axis BLDC (brushless DC) sensorless motor loop in 36 μs. It is also scalable and flexible; for example, control of BLDC, PMSM (permanent magnet synchronous motor) and stepper motors can be performed by a single SoC device.
In addition to their proven high performance, SmartFusion2 devices offer the flexibility inherent in FPGAs, including the ability to reconfigure pin assignments. This can be a big advantage and may help avoid the need to respin a PCB to accommodate a design change on the board.
Regarding the next part of the statement, which alleges that SoCs have limited internal memory, I won’t bore readers by quoting numbers to compare the different devices. Rather, I invite them to have a look at the SmartFusion2 devices on the Microsemi website and arrive at their own conclusions.
Further on in the article the author states “A further drawback is that, compared to the broad development toolsets provided by microcontroller manufacturers, there is significantly less support for firmware development in SoC motor drivers.” This is simply not true.
Firstly, for the motor control driver, Micro-semi offers extensive and proven motor control IP modules for free, dramatically reducing the firmware which needs to be developed. Without such IP, designers would need to write extensive firmware for a processor based solution.
Secondly, Microsemi offers great support with extensive application notes and examples, plus a dedicated team of engineers ready to help. From a local support perspective, ASIC Design Services offers in-house design specialists who are experienced with the technology and can assist customers to “get the design out the door”.
Microsemi’s SoC based motor control solutions comprise modular building blocks designed as standalone IP blocks. These include FOC transformation IP (Clarke, Park, Inverse Clarke and Inverse Park), PI controller, space vector modulation, core 3-phase PWM, rate limiter, position and speed estimator, encoder interface and stepper angle generator.
In addition to this, a fully modular IP suite is available that provides a quick plug-and-play approach to implement algorithms; easy porting and customisation through a block-based approach; precise algorithm for angle estimation in sensorless FOC; PWM with dead time protection and delay time insertion. These IP blocks are coded for efficient use of FPGA resources, are tested in simulations and on actual hardware, and are available as MATLAB models or VHDL code for FPGAs
IP blocks can be accessed by a Cortex-M3 microcontroller subsystem through an APB (Advanced Peripheral Bus) interface, and registers can be directly accessed by MSS (Microcontroller Subsystem) for controllability and observability. These provide benefits in terms of development and reduced time to market.
Finally, Microsemi offers a motor control kit to ease and accelerate development. It features dual-axis motor control on a single SoC FPGA, with IP scalable to multi-axis or high-RPM applications. The modular approach it adopts helps in customising the solution, as well as easing integration. Complex motor control algorithms are made easy to use and complete documentation is available with reference designs.
The system’s top level fabric code interfaces with MSS over APB interface for register read/writes. Each IP block is thoroughly tested in ModelSim and on actual hardware, provides close to 100% code coverage, and is available in VHDL format for fabric and in API format for MSS. MISRA coding guidelines have been used for software API development to ensure 100% linted code, and DO-254 recommended VHDL coding guidelines have been followed.
For more information contact Steve Santamarina, ASIC Design Services, +27 (0)11 315 8316, [email protected], www.asic.co.za
| Tel: | +27 11 315 8316 |
| Email: | [email protected] |
| www: | www.asic.co.za |
| Articles: | More information and articles about ASIC Design Services |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version