USB is ubiquitous. According to Intel, more than 6 billion USB products have been shipped to date. That is almost enough to equip every man, woman and child on the planet. As if that were not enough, with the performance enhancements in USB 3.0, the technology is likely to send other interfaces to the sidelines and accelerate its market penetration.
The new USB 3.0 standard (SuperSpeed USB) defines data transfer technology that is 10 times faster than USB 2.0. The added speed will open the door for a new round of consumer products and bring smiles to the faces of consumers who want to transfer videos to their smartphones. The higher-speed standard was driven by consumer demand, and from an end-user perspective, it is largely evolutionary. However, evolutionary does not mean ‘ho-hum.’ With a data rate of 5 Gbps and data throughput capability of greater than 200 MBps, the USB 3.0 interface is shaking up the data transfer world. It is faster than eSATA and FireWire, and it is likely to push these interfaces to the brink of extinction.
While PCI Express interfaces are internal buses, adapters are available that allow this technology to be used to transfer data from one PC to another. With the performance enhancements in USB 3.0, one can forego the adapters and transfer data with the throughput that would be obtained from using PCI Express. This is not to say USB 3.0 will replace PCI Express technologies – all shipping USB 3.0 hosts are currently PCI Express cards – but it highlights that USB 3.0 transfer rates give engineers in-the-box performance with a technology designed from the ground up for out-of-the-box applications.
The USB 3.0 standard is also shaking up the status quo in engineering labs. USB 3.0 architecture is fundamentally different from USB 2.0. It has a PHY layer – driven by the speed requirements – very similar to PCI Express technology. So engineers who are experts at testing and debugging USB 2.0 technology need to learn new skills. Also, at 3.0 speeds, engineers who are steeped in the digital world have to deal with microwave effects and they usually have no experience in the microwave realm. Digital designers now have to deal with signal path routing and impedance control, which are critical design requirements for USB 3.0. Receiver design is an order of magnitude more difficult because of the need to implement complex PLLs and active receiver equalisation.
One of the biggest changes designers face is the requirement to include spread-spectrum clocking (SSC) in all USB 3.0 products. SSC is required to overcome or reduce EMI issues. For device silicon, it is difficult to implement well-controlled SSC modulation for low-cost designs. Some motherboards improperly implement centre-spread SSC clocking, which violates the USB 3.0 specification requirements. Centre-spread profiles are centred on the nominal frequency and are modulated above and below by equal amounts, for example +2500/-2500 ppm. Most USB 3.0 devices are not compatible with systems that improperly implement centre-spread SSC. When consumers purchase host add-in cards and add them to a system that has a noncompliant system clock, they will be disappointed.
Device vendors have identified ways to work around this issue, for example by turning off SSC. The longer-term solution is to get system vendors to ensure they follow the SSC specification requirements for PCI Express and USB 3.0. For this reason it is important to address this issue within both the PCI Express community and the USB-IF compliance program.
Further complicating the task of designing USB 3.0-compliant devices is the standard’s backward compatibility requirement. As the USB standard has evolved, its data rates jumped from 1,5 Mbps and 12 Mbps (USB 1.1) to 480 Mbps (USB 2.0) and now to 5 Gbps (USB 3.0). Because each variant of USB has its own compliance test specification, the coexistence of different data rates and signal levels significantly increases device complexity and test requirements but allows backwards compatibility that gives consumers the flexibility to mix and match peripherals with different speeds and throughput rates. This flexibility is one of the major advantages of USB.
The tenfold increase in data rate in the USB 3.0 standard also creates new challenges in testing the transmitter, receiver and cabling system. To test SuperSpeed transmitter compliance and channel effect, engineers need a high-bandwidth oscilloscope to measure the transmitted waveform using compliance patterns. Because of the very long channel topologies allowed for USB 3.0, engineers are required to test transmitter and receiver compliance through the long channel. This means they will be testing their PHY characteristics through 3 metres of cable and an additional length of PCB trace, 13 cm for the host and 28 cm for devices.
The goal, of course, is for the engineer’s USB 3.0 product to pass the compliance tests to ensure electrical interoperability. However, passing compliance tests with one or more samples of a product is no guarantee that under different conditions or for different process corners, the product will still have no problems. Margin testing provides the additional confidence designers need.
Test and measurement companies, like Agilent, are critical to the testing process. The company provides the instruments to ensure engineers can characterise their components and devices according to the standard. Because Agilent is a contributing member of the USB Implementers Forum (USB-IF), it not only understands the specification, but helps to shape it.
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