Pipelining and re-timing are common design techniques often used to tackle timing hurdles faced when designing on FPGAs. Understanding the effects of these techniques on the design structure stimulates the study of their effects on power dissipation as well.
Pipelining and re-timing effects on the design structure
Pipelining a design adds more registers and reduces the depth of the combinatorial logic parts of the design. Re-timing shuffles registers through the combinatorial logic blocks but the number of added registers is less than in the case of pipelining. On the other hand, these techniques affect the fanout distribution for the internal nets. They lower the number of nets with a high fanout.
Pipelining and timing implications on power consumption
Added registers not only speed up the design but also help to reduce the switching activity as well as the glitching* propagation. This happens because the depth of the logic blocks and the number of glitchy high fanout nets are reduced. As a result, power consumption through the combinatorial logic is significantly reduced. The side-effect of adding registers is the increase of the clock load and the parallel execution that may increase the switching.
Figure 1 shows the difference of power consumption of a 16 bit multiplier mapped on Actel SX-A antifuse devices. As dynamic power consumption is proportional to the clock frequency, the difference becomes more important at higher frequencies.
Figure 1. Pipelined versus nonpipelined multiplier
How many pipeline stages are needed?
As for timing optimisation, the power consumption is reduced significantly with the first 1 or 2 stages and then becomes less significant. Figure 2 shows experimental results obtained for a 16 bit multiplier mapped on ProASIC, the flash-based FPGA, with various pipeline stages. As expected, the power consumption is slashed substantially for the first introduced pipeline stages.
Figure 2. Pipeline stages
Final recommendations
Pipelining and re-timing are recommended for both timing and power reduction on Actel antifuse and flash-based FPGAs. Even if the targeted timing is met, the recommendation is to seriously investigate pipelined configuration of arithmetic blocks and re-timing logic blocks when possible.
* Glitches are undefined and unpredictable switching activities that occur before a signal settles to its intended value.
Actel is represented in South Africa by ASIC Design Services. For further information contact Kobus van Rooyen, (011) 315 8316, [email protected]
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