Programmable Logic


Design environment supports low-power FPGAs

7 February 2007 Programmable Logic

The latest version of Actel′s Libero integrated design environment (IDE) offers full support for the company’s newest Flash-based field-programmable gate array (FPGA) solutions: the low-power Igloo family. The Libero IDE 7.3 also provides new easy-to-use features that will aid designers utilising the mixed-signal Actel Fusion programmable system chip (PSC) and ProASIC3/E families, says Actel.

It introduces innovative internal design functions, such as the new Libero block design flow, to lower FPGA development costs and enable users to reach design closure more quickly.

The enhanced IDE also combines advanced FPGA backend technology with best-in-class design software products from Synplicity, Mentor Graphics and SynaptiCAD. Optimised for Actel's new low-power Igloo FPGA family, the Libero IDE 7.3 software supports Igloo's three power modes - Flash*Freeze, low-power active and sleep. In Flash*Freeze mode, the Igloo devices achieve ultra-low power consumption of less than 5 μW.

These innovations build on the power-optimisation toolset available in Libero, including the SmartPower analysis tool, which allows users to characterise power consumption in the Actel Igloo devices.

Best-in-class tools and ease of design

Expanding the software support network for Actel FPGAs, the Libero IDE 7.3 includes the industry-standard Synplicity Identify 2.4.1, an RTL debugger, bundled for free in the Libero Gold edition. Combining these products in an easy-to-use package, Mentor Graphics and Actel expand the synthesis options for designers.

Further, SynaptiCAD and Actel worked closely to adapt the Waveformer Lite v11 testbench generation tool to support the unique architecture of Fusion, which includes analog, embedded flash and FPGA fabric on a monolithic PSC.

The Libero IDE 7.3 also introduces advanced internal design functionality with a block design flow and extends the backend timing and power analysis software with features, such as virtual clocks and bottleneck analysis, power initialisation with timing constraints and advanced power analysis for memory blocks. These features allow designers to rapidly reach design closure and characterise their FPGA design in the context of the overall system.

The Actel Libero IDE 7.3 Platinum edition is available on Windows and Unix platforms. The enhanced Libero IDE Gold edition (free) is available on Windows.



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