Programmable Logic


Versatile core offers a host of customer-defined features including improved application interface

29 June 2005 Programmable Logic

Actel's CorePCIF is the newest member of the company's popular PCI product family that also includes CorePCI and CorePCIX. This versatile FPGA PCI core incorporates netlist and register transfer level (RTL) versions with 33 and 66 MHz speeds, 32- and 64-bit bus widths, as well as target, master and target + master configurations all in one core.

Actel has additionally incorporated a host of customer-requested features, including the addition of FIFOs at the application interface, CardBus and Compact PCI support, a simplified plug-and-play interface for PCI and an improved user test bench. Actel's PCI-SIG-compliant family is suitable for a variety of market segments, including military, aerospace, industrial, computer and storage.

In addition to the feature set defined in the PCI 2.3 standard, Actel says that the new core offers features requested by a number of its 200+ PCI customers. Unique to Actel, the core is available in RTL, netlist and free evaluation versions, enabling designers to select the best format for their individual designs. By adding FIFO support, Actel enables an asynchronous backend and even higher throughput than is possible with PCI devices or IP that have a synchronous application interface. It also supports the CardBus standard.

The core also supports the Compact PCI standard, which is popular in a variety of markets including military and industrial. The core has a simplified plug-and-play interface for PCI due to its six base address registers (BARs), an improvement over CorePCI's two BARs. The core offers a fully updated user-configurable test bench, allowing users to build a system test bench to their specifications.

Actel claims it is the only company to offer industrial temperature grade 66 MHz PCI capability on a value-based FPGA - the ProASIC3 device. The core is capable of 66 MHz/64-bit, 33/32, 66/32 and 33/64 operation. A number of configurations are also available in both CorePCI and CorePCIF, including target, master and target + master.

For more information contact Maritz Botha, ASIC Design Services, +27 (0)11 315 8316, [email protected]



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