The test engineer increasingly plays the role of a consultant to designers, advising them on how to design testable boards.
As board densities increase and lead times shrink, manufacturing engineers perform more and more analysis of data for PCBs to ensure manufacturability. This is especially true of in-circuit test (ICT), where testability analysis can be the test engineer's primary activity. Some manufacturing facilities are using an advanced technique called 'early analysis' to respond quickly and effectively to the demands of today's boards. This article describes how early analysis can reduce the time and effort required for analysis, leading to a more responsive and efficient manufacturing organisation.
Analysis is driven by board complexity
Complex boards require more analysis to determine if they are manufacturable. While this is true for most electronics manufacturing processes, it is even more true for ICT. A brief review of the ICT process shows why.
ICT is the testing of individual components or small groups of components on an assembled board to verify the assembly process. This is generally done by placing the assembled board on a test fixture. The test fixture has metal probes that make contact with different nets on the board. Usually, a different fixture is used for each different board. The test fixture is connected to an ICT machine. The ICT machine tests components on board.
To prepare for ICT, the test engineer designs the fixture. The engineer also prepares a test program that runs on the test machine and conducts the actual test. Ideally, the fixture will make electrical contact with every net on the PCB. However, today's high-density boards have fewer and smaller locations available for test probes, so it is usually not possible to reach every net. If a large percentage of nets cannot be probed, then there may be no point in conducting ICT on the board.
Traditionally, the test engineer invests days or weeks in preparing data for a board. If, at the completion of that process, it turns out that the board will not be tested, then all that data preparation and analysis time was wasted. The only solution is to modify the board or hope for the best with a functional test.
A better alternative is for the test engineer to review the design before it is finalised and recommend any necessary design changes. Concurrent engineering (CE) and design for manufacturability (DFM) have been buzzwords for years. The reality is that CE and DFM are happening today, and the main method is for the design group to supply manufacturing, which then analyses the data and gives recommendations back to the design group (Figure 1).
The consultations result in boards that are more testable, but they leave the ICT engineer with even more data to review. Now, the test engineer may need to review two or more data packages for a given board. Even worse, some of the boards analysed will not be tested. So, while consultation works as a DFM method to increase testability, it also creates a large amount of analysis work for the test engineer. It is necessary to reduce the amount of analysis work required.
Early analysis
The solution is to change the kind of analyses that are performed. The old way is to prepare complete fixture data for every data set received. The new way is to first perform a quick, inexpensive analysis on all incoming data, before time-consuming data preparation is performed. Early analysis cannot just be a sloppy version of complete data preparation. Rather, it must answer a smaller set of questions with predictable precision. The questions asked must drive a manufacturing decision, such as:
* Whether to quote the job and how much to quote it for.
* Whether to proceed to manufacturing planning on the job.
* What manufacturing cost to assign to the job.
* When to schedule the job for production.
One can think of early analysis as an advanced report on the ground ahead. That report triggers a specific decision in the manufacturing process. In the case of ICT, there are two main questions for early analysis:
* Is ICT appropriate for this board?
* What changes should be made to improve testability?
Typically, the manufacturing decision is whether to perform ICT on this version of this board. The decision may also be whether to build the board as designed, given the testability.
Relatively little information is necessary to answer these two questions. A measure of testability can be determined from the percentage of accessible nets (the percentage of nets that can be contacted with a probe). A better measure is the percentage of part pins that are accessible. For example, the test engineer may want to know the percentage of two- and three-pin parts that have all pins accessible; the percentage of other parts that have at least 50% of pins available; and those that have at least 90% of pins accessible. Certain parts may be absolutely required for ICT to be worthwhile, so the test engineer will want to review accessibility of these parts pin-by-pin. Thus, the only pieces of information that are required to determine the appropriateness of ICT for a given revision of a board are:
* The percentage of accessible nets.
* The percentages of different part types that have most pins accessible.
* A list of pins that are accessible for each part, pin-by-pin (Figure 2).
A little more information is required to determine changes that would improve testability. The test engineer will want a list of opportunities to make inaccessible nets accessible, such as those covered by a solder mask, which can be unmasked, and test pads that are too small to probe, but which can be enlarged. This is much less work than is required to prepare a test fixture and test program. In fact, early analysis as just described for ICT can be done in an hour while full-blown ICT preparation can take days or even weeks.
How to perform early analysis
Early analysis is most valuable when it is done early enough to affect the design. Do early analysis as early as possible! Particularly for contract assemblers and testers, this is a challenge: contracts are now bid on and awarded so quickly that quotes must be issued as soon as possible after data arrives - sometimes the same day. There is often no opportunity to ask for a second data package. You must use what you get or quote blind. What you often get is just Gerber data (the data used to fabricate the board), which describes the exact circuit pattern on each layer of the board. Thus, successful early analysis must be able to use Gerber data alone, regardless of other data formats supported.
Since early analysis must be done quickly, the process must be automated. If possible, a data preparation software program specially designed for early analysis should be used. At a minimum, a fixturing program or another system that can produce an appropriate testability report can be used. Analysing the data manually will not work since the process will take too much time and effort, and is too prone to error.
One crucial issue is to identify solder mask problems that prevent nets from being tested. Since the solder mask is often the last part of the design to be finalised, it represents the last opportunity to address net access. Often, solder mask can be easily modified with no effect on board performance or durability. Thus, accurate solder masks information must be used, and it must be processed correctly. It is essential that solder mask information be processed automatically and reliably. If the test engineer spends time massaging or double-checking the solder mask information, early analysis will fail to save the analysis effort.
There is not time to prepare a testability report by cutting and pasting different pieces together. The testability report must be as it is produced from the data preparation program. It must contain the information necessary to answer our two questions and little else. Ideally, to account for different manufacturing environments, the report should be customisable, for example, to account for different allowable probe spacing and minimum size of probable features. The test engineer presses a button and receives a report that can be e-mailed or faxed to the designer 'as is'.
When early analysis is performed, all boards are analysed as the first phase of test design. If the decision is to proceed with ICT, the data preparation performed for early analysis is re-used in fixture design and test program generation.
Early analysis reduces costs
By reducing the amount of time spent on data analysis, early analysis can save days or even weeks on a typical board. But, there are two other cost saving opportunities that are at least as great: increased product reliability and decreased fixture cost. Early analysis increases the proportion of boards that can be tested and increases the test coverage of boards that are tested. Better ICT means better detection of latent failures and greater product reliability. By using accurate solder mask information, early analysis reduces probes placed on unusable locations and, thus, fixture rework. Early analysis can compare a new revision of a board to an existing fixture and recommend changes to minimise or eliminate a fixture revision or even to add a new fixture.
Conclusion
The test engineer's job certainly has not been getting easier. Higher-density boards, BGAs (ball grid arrays) and other new package types suggest the future will only be more complex. The test engineer increasingly plays the role of consultant to designers, advising them on how to design testable boards. This new concurrent engineering role results in more data sets requiring more analysis. Taming this avalanche of data requires new tools and new approaches. Early analysis brings testability analysis costs under control and improves the entire ICT process.
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