Design Automation


PCB design combining manual and automatic routing

25 June 2008 Design Automation

The PADS Router from Mentor Graphics is an advanced, interactive trace editor that is available to printed circuit board designers as part of the PADS product flow of electronic engineering software design tools.

The PADS Router utilises Latium technology to deliver efficient initial and post trace modification capabilities.

Interactive routing

Most routing solutions today consist of one of two methodologies – manual routing and automatic routing.

Manual routing means each trace is placed by ‘tracing’ the exact pathway defined by the mouse cursor; every corner is defined usually by clicking the mouse and the system flags design rule clearance violations via a graphic indication.

Autorouting is just the opposite, where design rules are defined and the design is submitted to the system which proceeds to route without interaction; results are then reviewed post route.

Interactive routing is a technique that gives the designer the control of manual routing, but with the speed of autorouting. The PADS Router is an interactive routing environment which utilises a ‘push-n-shove’ methodology to allow seamless initial trace placement and post trace modifications.

Traces and vias placed on a printed circuit board (PCB) design dynamically shift their locations as new traces and vias are introduced into an area, allowing the designer to review an area before deciding to commit to a particular pattern. The PADS Router recognises and utilises the PADS Layout constraint hierarchical structure to ensure the proper constraint definitions are maintained during trace placement.

Users can easily change layers while the router maintains the proper spacing on all items, on all layers, in realtime. Via definition can also be incorporated as part of the required constraints, so that only particular vias are inserted as the trace bridges multiple layers.

The PADS router also manages high speed constraints associated with minimum and maximum length, and matched lengths. Constraints can be specified in both the schematic capture and layout programs, and the router responds with the same realtime feedback behaviour.

Signals requiring special coupling can have constraints set and maintained automatically while the trace is placed in the design. Adjacent traces maintain the proper clearance while the coupled traces are placed, resulting in minimal resistance throughout the entire trace addition process.

Trace addition

Users can begin trace additions by selecting the appropriate tool in the software. This places the software in a verb/object mode that allows an action to be applied to any object selected. This provides users with a single selection route mode, so traces can be placed quickly, one after another.

Once in this mode users select either a device pad or an unrouted connection. By selecting the device pad, a trace is generated immediately with the proper width extending from the selected device pad (Figure 1). As the cursor is dragged through the design, the PADS Router dynamically clears obstacles directly in the path of the trace being placed.

Figure 1
Figure 1

If users choose to select an unrouted connection, the PADS Router may start on either side of the pin-pair depending on how close the cursor is to either pad. The PADS Router attempts to auto-connect the trace being placed to the pad nearest to the cursor when selected (Figure 2).

Figure 2
Figure 2

Pin pair orders can be modified ‘on the fly’ while placing traces, giving users maximum routing flexibility. On nets that require specific routing requirements, there are routing controls that provide restrictions on inter-connecting pads, so a specific order is maintained. There are even special modes, such as Mid-Driven, Serial Source and Parallel Source, that can be enabled to produce special routing patterns depending on the net geometry requirements.

As traces are placed in the design (Figure 3), regardless of the defined net constraints, the PADS Router has multiple choices as to how it handles those obstacles, including:

* Routing over obstacles with trace segments automatically removed.

* Having violating obstacle locations adjusted to compensate for the additional traces.

* Having DRC set to inform the user any time they place traces too close to other items whose constraints have not been maintained.

Figure 3
Figure 3

Having multiple choices in trace placement adds to the flexibility that makes the PADS Router engine highly efficient.

Trace modifications

The PADS Router not only allows initial trace placement but it also allows trace modification (Figure 4). Trace data can be completely rerouted while still utilising the PADS Router’s power to push-n-shove placed obstacles completely out of the way. Users simply select the trace segment they wish to begin the modification at, place the new desired trace segments and then reconnect back into the existing trace to complete the modifications. All the while the PADS Router is reviewing the trace constraints to ensure that all modifications still conform.

Figure 4
Figure 4

The PADS Router can shove not only individual trace/via obstacles but multiples as well (Figure 5). If a trace needs to be adjusted in an area where an entire bus exists, the user simply selects the trace and stretches it to the desired location. Any adjacent traces will automatically adjust to accommodate the new location. If 45° corners were utilised in the trace being moved, all the associated 45° traces will be maintained after the adjustment as well. If vias need adjusting, users simply select the desired via and drag it to a new location with traces automatically adjusting to the new location.

Figure 5
Figure 5

Conclusion

PCB design layouts, whether simple or dense, can benefit from the PADS Router’s power, and intuitive methodology. As design constraints become more prevalent in everyday designs, PCB designers can no longer keep track of every net, class or length based rule during trace placement. The PADS Router overcomes these obstacles, allowing the circuit board designer to focus on resolving other more complex design issues.

For more information contact ASIC Design Services, +27 (0)11 315 8316, [email protected], www.asic.co.za



Credit(s)



Share this article:
Share via emailShare via LinkedInPrint this page

Further reading:

MPLAB PICkit Basic
ASIC Design Services Design Automation
To make its robust programming and debugging capabilities accessible to a wider range of engineers, Microchip Technology has launched the MPLAB PICkit Basic in-circuit debugger.

Read more...
Case Study: Siemens Valor automation solution
ASIC Design Services Editor's Choice Manufacturing / Production Technology, Hardware & Services
Electronics manufacturer BMK used Siemens Valor to enhance accuracy and speed up bill-of-materials quotations.

Read more...
Accelerating RF PCB design in a 5G world
ASIC Design Services Editor's Choice Design Automation
Billions of IoT devices coming online in the coming years will require RF design capabilities that support ultra-fast 5G speeds.

Read more...
XJLink-PF40 JTAG controller
ASIC Design Services Test & Measurement
XJTAG, a specialist in electronic testing, has released its new XJLink-PF40 JTAG controller together with version 4 of its popular PCB software testing suite.

Read more...
NECTO Studio has been updated
Design Automation
NECTO Studio V7.1 IDE from MIKROE now includes full programmer and debug support for Microchip tools and also adds support for Microchip’s SAM MCU and STMicroelectronics’ STM32L4 series of ultra-low-power MCUs.

Read more...
Microchip SoC FPGA
ASIC Design Services DSP, Micros & Memory
Microchip Technology introduced the RT PolarFire SoC FPGA, the first real-time Linux capable, RISC-V-based microprocessor subsystem on a proven RT PolarFire FPGA platform.

Read more...
Development kit for MIL-STD-1553 dual transceiver
ASIC Design Services Telecoms, Datacoms, Wireless, IoT
Holt Integrated Circuits has announced the introduction of ADK-1592, a development kit designed to help customers interface Holt’s recently announced HI-1592 radiation hardened transceiver.

Read more...
Development kit for programmable 16-channel low-side driver
ASIC Design Services DSP, Micros & Memory
Holt Integrated Circuits has announced the introduction of ADK-84216, a development kit designed to demonstrate the features of Holt’s recently announced programmable 16-channel low-side driver, HI-84216.

Read more...
Microchip’s RTG4 FPGAs achieve highest space qualification
ASIC Design Services DSP, Micros & Memory
QML Class V is the highest level of qualification for space components, and a necessary step to satisfy mission-assurance requirements on the most critical space missions such as human-rated, deep space, and national security programmes.

Read more...
Altium provides free training
Design Automation
There is no longer any excuse not to master Altium Designer with the company now offering both advanced instructor-led three-day training and an on-demand video series.

Read more...