Underscoring its commitment to deliver and support power-efficient solutions, Actel has enhanced its Libero integrated design environment (IDE) to further ease the system-level design process when using its field-programmable gate arrays (FPGAs).
With SmartDesign, a new design entry capability that enables users to design at a higher level of abstraction, Actel says that its Libero IDE v8.0 significantly reduces FPGA design and development time, thus speeding customers' time to market. The enhanced tool suite supports all the company's FPGAs, including the flash-based, low-power ProASIC3 and 5 μW Actel IGLOO FPGAs, as well as the company's single-chip Actel Fusion programmable system chip (PSC), a mixed-signal power management FPGA.
SmartDesign lets users visually create and then automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components. The graphical block-based design entry supports prefabricated blocks from Actel's extensive DirectCore and SmartGen IP libraries. It also supports custom blocks created in HDL or Synplify DSP and processor subsystems created with Actel's CoreConsole tool.
SmartDesign block-based system-level design environment
An innovative SmartDesign capability enables source file components, such as SmartGen- and CoreConsole-configured IP and processor cores, HDL modules, Actel cell macros, and Libero-created blocks, to be visually brought together onto a white-board 'canvas' in a block-diagram view. A 'catalogue' provides an extensive list of IP, macros, HDL templates, and bus interfaces that can be selected and dragged and dropped onto the canvas. Thus, SmartDesign facilitates real design re-use and paves the way for future block capture designs using system Verilog, DSP, mixed hardware/software blocks, and more.
While capturing a design using SmartDesign, a 'SmartGuide' function suggests compatible bus interfaces and IP cores that may be appropriate for the design. This same function, serving as a design rule checker, ensures the connections are correct by construction. Upon completion, a synthesis-ready HDL source file is created. With many connections automatically made by the SmartConnect function within SmartDesign, the Libero IDE v8.0 enables designers to save time and minimise errors.
New features ease Fusion power management designs
Actel's award-winning mixed-signal FPGA family, Fusion, receives additional support in Libero IDE v8.0 with the FlashPro 6.0 software update. Used with FlashPro programmers, this new version of the software further eases the programming of Actel's IGLOO/e, ProASIC3 and Actel Fusion devices. A new feature in FlashPro, called FlashPoint, increases the flexibility in design finalisation by allowing the user to modify and edit the FlashROM security settings independent of Libero or Designer. This saves the user from having to re-run the design through synthesis, place and route, and program file generation, significantly reducing overall design time. For Fusion, FlashPro's FlashPoint feature further supports the independent programming of the Fusion Embedded Flash Memory. Users can efficiently reprogram the power management analog and memory system code stored in the embedded flash memory.
The Actel Libero IDE 8.0 Platinum edition is available on Windows and Linux platforms for a fee, and a limited feature Gold edition is available on Windows for free.
| Tel: | +27 11 315 8316 |
| Email: | info@asic.co.za |
| www: | www.asic.co.za |
| Articles: | More information and articles about ASIC Design Services |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version