Actel has released a new version of its Libero integrated design environment (IDE) with new features intended to increase the flexibility, efficiency and performance of designs based on the company's field-programmable gate arrays (FPGAs).
In this Libero IDE 7.2 release, enhanced SmartGen, SmartTime and SmartPower tools offer new capabilities for IP generation to support the Actel Fusion programmable system chip (PSC) offerings. It also offers advanced timing and power analysis functionalities for designers using the Actel Fusion, ProASIC3 and RTAX-S families.
'As more system engineers turn to FPGAs, the Libero IDE 7.2 allows these designers to leverage the capabilities of the Fusion platform whether they are coming from a SoC, mixed-signal, discrete or analog design environment', said Jake Chuang, a senior director at Actel.
For a large variety of commonly used IP functions, the SmartGen tool provides users with design automation functionality to import existing cores and create new ones for their Fusion-based designs. New features include a sample sequencer, a sample sequence configurator and a visual phase-locked loop (PLL) configurator. Further, the state management capability that audits module changes and dependencies can now pass this information directly to Libero, allowing the designer to update all dependent modules with one click. SmartGen now also supports the direct update of nonvolatile memory for analog system blocks, reducing or eliminating lengthy iterations through synthesis.
Actel's SmartTime feature provides static timing analysis capabilities based on industry standards, such as Synopsys Design Constraints (SDC), as well as new visual constraint dialogues, easing the transition from ASICs to mixed-signal FPGAs. Enhancements to Actel's SmartPower power analysis tool enables users to perform detailed power-consumption analysis, helping to conserve power, cut costs and improve design reliability.
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