Actel's new technology, named Fusion, is ushering in the era of the programmable system chip (PSC). The Actel Fusion technology combines analog capability, Flash memory, and FPGA fabric in a monolithic PSC. This gives designers, for the first time, a programmable logic solution incorporating analog and Flash memory components.
The race to the programmable system chip
End applications continue to demand increased flexibility, configurability, and performance, along with reduced power demands, board space, and cost. Following increasing pressure for horizontal integration of analog, memory, logic, and soft microcontroller (MCU) implementations in a single chip, analog, microcontroller, and ASIC suppliers are all moving to add configurability to their product lines. In this race to PSC solutions, analog suppliers have added processors to their solutions. Microcontroller suppliers, seeing their mask costs rise, are looking to configurability to service the same solution space with a smaller product catalogue. ASIC suppliers, who continue to see their design start numbers impacted by increased mask costs and increased time to market pressures, are adding embedded Flash memory to integrate additional functionality (Figure 1).
As the race to develop PSC solutions heats up, FPGA suppliers have a leg up on the competition because programmable logic has proved the most difficult of these technologies to master. While a large number of FPGA suppliers have entered the market over the years, only a handful of suppliers still compete today due to several barriers to entry that continue to keep the number small. One barrier is a need for hardware that includes the development of efficient, flexible, and high-performance programmable fabric. On the software side, there is very large tool overhead to support design development, verification, validation, and programming.
Having solved the complex issues surrounding programmable logic design and development, FPGA suppliers have another advantage when they integrate analog and Flash memory, in that this integration has already been proven in ASIC and MCU technologies.
Real-world systems require multiple silicon technologies
Actel Fusion technology presents new capabilities for system development by allowing designers to use the same silicon for a variety of applications and/or quickly adapt to rapidly changing standards. Figure 2 shows a typical real-world application and many of the technologies used in the solution.
As shown in Figure 2, the main processor is supported by both volatile (SRAM/DRAM data memory) and nonvolatile (Flash) memory. Compared with ROMs and PROMs, the programmability and price points of Flash have made it the preferred code storage solution. As seen, the system FPGA/ASIC resides next to the processor to offload the processor and add the customer's intellectual property (IP) to the board. Processing is moving from the analog domain to the digital. More systems now must communicate with analog signals, increasing the demand for integrated analog. The real world is analog, and higher levels of integration take digital solutions closer to the analog interface.
Many boards have a host of common housekeeping issues, including power and clock management. Controlling system power has become an important aspect of today's applications, as many components now run from multiple power supplies with specific sequencing requirements. Additionally, these supplies must be monitored for fluctuations that can put volatile resources in undetermined states.
Embedded-flash process supports PSC
Of the FPGA technologies in the market today, the Actel Flash process is considered best suited for implementing a PSC. By combining both Flash and high-speed CMOS processes in a single chip, these devices offer the best of both worlds. The high-performance CMOS is used for building RAM resources. These high performance structures support device operation up to 350 MHz. Additionally, the Actel advanced 0,13 mm Flash process incorporates high-voltage transistors and a high-isolation, triple-well process. Both of these are suited for the Flash-based programmable logic and nonvolatile memory structures.
High-voltage transistors support the integration of analog technology in several ways. They aid in noise immunity so that the analog portions of the chip can be better isolated from the digital portions, increasing analog accuracy. Because they support high voltages, Actel Flash FPGAs can be connected directly to high-voltage input signals, eliminating the need for external resistor divider networks, reducing component count, and increasing accuracy. By supporting higher internal voltages, Actel's advanced Flash process enables high-dynamic range on analog circuitry increasing precision and signal/noise ratio. Actel Flash FPGAs also drive high-voltage outputs, eliminating the need for external level shifters and drivers. The unique triple-well process enables the integration of high-performance analog features with increased noise immunity and better isolation. By increasing the efficiency of analog design, the triple-well process also enables a smaller overall design size, reducing die size and cost.
Actel Fusion integration
Actel Fusion technology represents a revolutionary new approach to PSC development and is the first to integrate mixed-signal capabilities with Flash memory and FPGA fabric in a monolithic PSC. Figure 3 is illustrative of the type of functionality that can be integrated into a typical device based on this technology. The unprecedented level of integration offered by the Actel Fusion technology will enable system designers to remove multiple devices from their systems by integrating the functionality into a Fusion-enabled PSC, greatly simplifying board and system design. An Actel Fusion-based device can also offload peripheral tasks from the main processor, reducing microprocessor performance and development requirements. Further, the combination of reduced component count and the live at power-up, single-chip attributes of this technology enables significant power savings.
As Figure 3 illustrates, the Actel Fusion technology is a single-chip configurable processor solution, enabling the ultimate soft-processor implementation platform. A microcontroller core (ARM7 or 8051) can be implemented in logic gates with the on-chip Flash to support code and data space implemented in on-chip RAM. The ability to add peripherals directly to the processor bus further enables single-chip, custom SoC development.
Actel Fusion technology stack
To manage this unique level of integration, Actel developed the Fusion technology stack (Figure 4). This layered model offers a flexible design environment, enabling design at very high and very low levels of abstraction. Fusion peripherals include hard analog IP and hard and/or soft digital IP.
Peripherals communicate across the FPGA fabric via a layer of soft gates - the Fusion backbone. Much more than a common bus interface, this Fusion backbone integrates a micro-sequencer within the FPGA fabric and configures the individual peripherals and supports low-level processing of peripheral data. Fusion applets are application building blocks that can control and/or respond to peripherals and/or other system signals. Applets can be rapidly combined to create large applications. The technology is scalable across devices, families, design types, and user expertise, and supports a well-defined interface for external IP and tool integration.
At the lowest level, Level 0, are Fusion peripherals. These are configurable functional blocks that can be hardwired structures such as a PLL (phase-locked loop) or analog input channel, or can be implemented in soft gates as a UART or two-wire serial interface. The Fusion peripherals are configurable and support a standard interface to facilitate communication and implementation.
Connecting and controlling access to the peripherals is the Fusion backbone, Level 1. The backbone is a soft-gate structure and is scalable to any number of peripherals. The backbone is a bus and much more; it manages peripheral configuration to ensure proper operation. Leveraging the common peripheral interface and a low-level state machine, the backbone efficiently offloads peripheral management from the system design. The backbone can set and clear flags based upon peripheral behaviour and define performance criteria. The flexibility of the stack enables a designer to configure the silicon, directly bypassing the backbone if that level of control is desired.
One step up from the backbone is the Fusion applet, Level 2. The applet is an application building block that implements a specific function in FPGA gates. It can react to stimuli and board-level events coming through the backbone, or from other sources, and responds to these stimuli by accessing and manipulating peripherals via the backbone or initiating some other action. An applet controls or responds to the peripheral(s). Applets can be easily imported or exported from the design environment. The applet structure is open and well-defined, enabling users to import applets from Actel, system developers, third parties, and user groups.
The system application, Level 3, is the larger user application that utilises one or more applets. Designing at the highest level of abstraction supported by the Actel Fusion Technology stack, an entire FPGA system design can be created without any HDL coding. Implemented in FPGA gates, the application can be easily created by importing and configuring multiple applets.
An optional MCU enables a combination of software and HDL-based design methodologies. The MCU can be on-chip or off-chip as system requirements dictate. System portioning is very flexible, allowing the MCU to reside above the applets or to absorb applets, or applets and backbone, if desired.
The Actel Fusion technology stack enables a very flexible design environment. Users can engage in design across a continuum of abstraction from very low to very high. Figure 5 illustrates a physical view of the Actel Fusion technology.
Fusion tools
The increased level of integration afforded by PSC solutions adds new complexity and requirements to the development tools. Some of the key required tool features at this level are as follows:
* High level of design productivity.
* New methods for rapid application generation.
* Hardware/software co-verification.
* Bus-based communication.
* Device/system modelling and design partitioning.
* Innovative debugging capability.
To support this new ground-breaking technology, Actel is developing a series of major tool innovations to help maximise designer productivity. Implemented as extensions to the popular Actel Libero Integrated Design Environment (IDE), these new tools allow designers to easily instantiate and configure peripherals within a design, establish links between peripherals, create or import building blocks or reference designs, and perform hardware/software verification. This tool suite will also add a comprehensive hardware/software debug capability as well as a suite of utilities to simplify development of embedded soft ARM and 8051 processor-based solutions.
Summary
Companies in many technology areas are pursuing the development of a programmable system chip. Due to the barriers inherent in developing efficient, easy-to-use, cost-effective programmable logic, FPGA suppliers are better positioned to develop a PSC solution. Leveraging expertise gained in developing its successful line of Flash FPGAs, Actel is in a unique position to integrate analog, Flash, logic, FPGA fabric, and soft MCU into a monolithic programmable system chip. The Actel Fusion technology stack provides a flexible and structured means of utilising this unprecedented level of integration, facilitating IP re-use and rapid design development. Actel Fusion tools provide an easy-to-use graphical interface to simplify development.
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