Actel has announced that its free Libero Gold integrated design environment (IDE) now provides expanded device support for designs up to one million gates. Users need only download and install a small service pack, the Libero 7.0 IDE Service Pack 1 (SP1), to their existing Libero 7.0 IDE software to immediately start developing one million-gate designs using Actel's FPGAs.
This free support covers all Actel single-chip device families, including the company's ProASIC3 and ARM7-enabled ProASIC3 FPGA families, and its new mixed-signal FPGA, the Actel Fusion programmable system chip (PSC). For the latter, Libero 7.0 SP1 also provides enhanced SmartGen Fusion IP peripheral generation flows that streamline the configuration of analog System Builder Components. In addition, SP1 includes enhanced algorithms that improve the place-and-route efficiency and quality of results for Actel's high-performance, antifuse-based Axcelerator FPGAs.
The Libero IDE Gold software contains all the tools of Libero IDE Platinum, except Palace AE Physical Synthesis, and WaveFormer Lite Reactive Test Bench and VCD import. Libero IDE 7.0 SP1 is available as a free software download from Actel's website.
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