Cadence Design Systems has introduced the OrCAD Signal Explorer product, the latest advance in its scalable, personal productivity product line. This latest addition to the OrCAD product line features new PCB-level topology exploration and signal integrity (SI) analysis technology.
Bringing SI analysis and validation to the design process early allows designers to use circuit and PCB topology exploration to facilitate increased circuit reliability and drive known good requirements into the back end. With OrCAD Signal Explorer, Cadence says that designers can analyse and validate topologies against SI requirements to help minimise potential SI-related issues that can result in fewer re-spins and shorter lab debug time. This can mean shorter design cycles and faster time to market.
"As users of Cadence's PCB SI products we are pleased to see Cadence leverage its industry-proven SI technology to enhance its OrCAD product line," said Jacob Bast, principal engineer for Netezza. "OrCAD's newest technology will provide the OrCAD users an SI driven methodology that will help reduce prototype spins and time spent on PCB de-bug in the lab."
"OrCAD Signal Explorer continues to strengthen the OrCAD product line by offering scaleable, cost-effective solutions for our customers. We are committed to providing OrCAD customers with the tools they need to meet their current and emerging design challenges, project schedules and bring their products to market," said Steve Kamin, Cadence director of the OrCAD product line.
OrCAD Signal Explorer is sold as a standalone product in the OrCAD 10.5 release. This technology provides easy migration from the OrCAD product line to the Cadence Allegro 200 Series, and on to the Allegro 600 Series, without the need to translate design databases or change use models.
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