To minimise the overall distance that a signal travels, PCB designers usually place the switching IC (FPGAs or ASICs) in roughly the centre of the board.
Of course, it is also possible to minimise signal losses between the outside I/O and the switch devices by placing them close together, but that only worsens signal integrity from the ASIC or FPGA to the backplane.
To help with signal losses at 56 Gbits/s, many engineers are moving to 4-level pulse-amplitude modulation (PAM4), which doubles the data rate for a given signalling rate versus NRZ. Thus, a 14 GHz clock can deliver 56 Gbits/s using PAM4, but there’s a problem. The signal amplitude (eye height) of a PAM4 signal is one-third that of an NRZ signal. That creates a trade-off between signal loss and sensitivity to noise.
With flyover, high-speed signals are not routed through lossy PCBs, vias, and other components. Rather, they are routed through ultra-low-skew twinax cable assemblies in system. This minimises signal degradation while also eliminating the need for more expensive PCB materials.
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