Circuit complexity continues to soar despite the fact that IC design tool capabilities remain fully one to two generations behind. Arguably, a prime contributor to the design productivity gap today is conventional synthesis technology.
Some of the problems found in using current synthesis methodologies include:
* The maximum synthesizable block size is about 1/100th of the overall design size and is becoming a smaller percentage of the chip with each silicon generation.
* The work-around solutions to manage small block sizes require inordinate amounts of manual scripting, drastically reducing design quality and productivity by the engineer.
* The more partitioned blocks there are in a design, the worse delay QoR becomes because the synthesis tool cannot 'see' as many optimisations.
* Breaking designs according to arbitrary gate count limits is hard for a logic designer - who naturally breaks a design into functionality and timing.
* While top-down synthesis delivers the best possible delay QoR, it is limited in memory and runtime to handling smaller pieces of the entire design.
* IP, datapath, analog/mixed signal, and, in the future, embedded FPGA are all examples of elements of a design that should have special handling in synthesis, regardless of block size.
* 20M gate complexities (or larger) cannot be synthesised well with today's 'divide and conquer,' bottom-up approach.
To address these shortcomings of traditional synthesis approaches as applied to high-complexity ICs, Synplicity developed a new MultiPoint synthesis technology for multimillion gate SoC (system-on-a-chip) and PSoC (programmable system-on-a-chip) devices. By providing a high-productivity design methodology that is scalable to tens of millions of gates, the MultiPoint technology addresses design challenges that are emerging as application specific integrated circuits (ASICs) and programmable logic devices (PLDs) become more complex.
In MultiPoint synthesis, Synplicity has combined new technology advances with the best of existing design methods to provide for the best timing and area results with low runtime. The technology uniquely and automatically creates Interface Logic Models (ILMs) based upon user-defined 'compile points' (Table 1) or instructions to the synthesis tool for modelling and synthesizing a particular portion of the design.
By thus reducing the design data for these modules, MultiPoint technology reduces memory requirements needed to synthesize large designs (Figure 1).
This means a designer can hierarchically synthesize their design based on functionality and timing, not an arbitrary gate count limit. MultiPoint technology optimises across design partitions using the same information needed for a top-down synthesis flow, enabling the highest design performance. Additionally, ILMs can be written out for any netlist or synthesized design, even from third-party tools. The use of ILMs and compile points in an overall synthesis flow is illustrated in Figure 2.
MultiPoint technology incorporates a unique, difference-based incremental synthesis approach (Table 2), eliminating the need for re-synthesis, common with time-stamp-based incremental flows, by only re-synthesizing design entities that will have a different gate-level netlist due to code or constraint changes. This minimises the impact of changes by using constraints and RTL to determine what must change. Design stability is ensured by way of locked compile points that isolate changes to the module(s) of interest.
With its ability to automatically model the IP and use the timing information for synthesis, the MultiPoint flow also eases intellectual property (IP) integration into a design. For example, MultiPoint technology optimises logic both inside an instantiated IP block and in its adjacent modules without impacting port assignments for the IP core. For designs with replicated logic or IP blocks, MultiPoint synthesis allows one to control how each unique instance is treated in terms of boundary optimisations without the runtime penalty of re-synthesizing each instance.
For ASIC design, MultiPoint technology delivers a methodology for implementing highly complex designs. With ASIC designs exceeding two million gate densities that includes some form of IP or replicated logic becoming more common, existing top-down or bottom-up methodologies are inadequate. The traditional bottom-up design flow, or synthesizing lower modules of a design before synthesizing the upper modules, can require many cumbersome scripts and time budgeting, and can inhibit boundary optimisation and lead to sub-optimal design performance. Similarly, synthesizing the design hierarchy all at once in a top-down flow is ideal for delivering the best design performance, but is limited by the memory capacity of the compute, as well as long runtimes for synthesizing the entire design. With its unique incremental approach and use of compile points and ILMs, MultiPoint technology produces the Quality of Results (QoR) and ease-of-use of top-down flows, as well as the stability, fast runtimes, and capacity of a bottom-up flow.
Likewise, programmable device complexity abounds. Emerging PSoC devices include capabilities such as complex I/Os and embedded processors, and offer up to 10 million PLD-gate capacities. With this increase in complexity come design challenges that are now equivalent to those for ASIC devices. Programmable logic vendors are responding to customer needs with new incremental place and route capabilities. The technology's new and complementary synthesis capability creates an effective and complete incremental flow for high-complexity FPGA designs. The MultiPoint flow can significantly improve runtimes for both synthesis and place and route.
MultiPoint technology represents the optimal compromise between top-down and bottom-up design approaches. The technology delivers an automated, high-productivity incremental synthesis solution for large designs in terms of runtime, quality of timing and area results, and integration of intellectual property blocks.
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