Clear Logic has announced availability of production quantities of the first member of its Liberator ASIC family. According to the company, the 50 000 gate Liberator CL10K50V is the world's first device to offer customers the low unit costs and power consumption of masked-ASICs with the quick turn-around, flexibility, and low NRE of an FPGA-based design flow.
The Liberator CL10K50V ASIC is prototyped using a re-programmable FLEX 10K50V FPGA and standard third-party FPGA design tools. Since the prototype is re-programmable, designers may iterate the design as many times as desired with no extra costs, says Clear Logic. The FPGA is the final prototype; there is no foundry prototyping, and the only prototyping cost is the cost of the FPGA.
Liberator ASICs are created entirely over the Internet with no design 'conversion' and no customer-side engineering. The designer simply submits the FPGA prototype bitstream to Clear Logic's web site, www.clear-logic.com, and Clear Logic migrates the FPGA prototype bitstream directly to the Liberator architecture, using its proprietary ClearShot bitstream migration software. Clear Logic generates simulation models, device configuration instructions, and test vectors, and sends the simulation models to the engineer within 24 hours.
The company says that it ships free configured sample devices within four to five weeks, and production volumes are shipped within five to six weeks of receiving an order.
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