New from Analog Devices is the AD9554 multi-service adaptive quad-channel clock translator with clock multiplier, which provides jitter cleanup and synchronisation for many systems, including synchronous optical networks (SONET/SDH). Its embedded cross-point switch at the input provides greater flexibility and lower cost of ownership than maintaining different clocking configurations of multiple parts.
The chip dissipates only 940 mW of power while generating up to eight output clocks over an output range of 430 kHz to 941 MHz, synchronised to four 2 kHz to 1 GHz external input references, with a loop bandwidth as low as 0,1 Hz. The four analog-digital phase-locked loops (ADPLLs) enable the reduction of input jitter or phase noise associated with the external references.
The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low-jitter output clock even when all reference inputs have failed. The IC has adaptive clocking capability that allows the user to dynamically change the DPLL divide ratios while they are locked.
Output jitter is 250 fs over the 50 kHz to 80 MHz range and 350 fs over the 12 kHz to 20 MHz range.
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