32-bit quadrature counter
27 June 2012
Analogue, Mixed Signal, LSI
LSI/CSI recently expanded its line of encoder interface/quadrature counter ICs with the addition of the LS7366R, an integrated circuit for decoding and counting quadrature clocks directly from incremental encoders. It provides a dedicated solution to position and displacement tracking at 40 x 106/sec line rate (at 5 V) from the encoder and a count limit of 232.
The device can also operate with non-quadrature clock signals and provides various counting modes for signal conditioning. Equipped with a serial peripheral interface (SPI) port, it operates over the voltage range of 3 V to 5,5 V. Programming of the LSR7366R and all communications between itself and a host controller are made with four simple instructions: READ_reg, WRITE_reg, LOAD_reg and CLEAR_reg.
The functional modes are controlled with two bytes of data written into two on-chip registers. The configurable modes are: quadrature/non-quadrature count inputs; quad cycle resolution selection by factor of x1, x2 or x4; modulo-n counting for programmable frequency generation; range-limit counting for limit switch emulation; single-cycle counting; and 1 Byte, 2 Byte, 3 Byte and 4 Byte counter modes with auto-adjust of I/O byte count.
The count-related status is stored in a status register. A 32-bit input register along with a 32-bit comparator are provided for comparing a target value with the instantaneous count. Two maskable output flags are also provided for signalling count-related events. The index and the quadrature inputs are digitally filtered for noise suppression. The IC is offered in 14-pin DIP, SOIC and TSSOP packages.
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