High performance single-FPGA turbo code solution
4 July 2001
Programmable Logic
Xilinx has expanded its XtremeDSP initiative by announcing the availability of turbo convolutional encoder and decoder LogiCORE IP products for its Virtex and Virtex-II FPGA families.
Designers can now integrate one or more high-performance turbo code modules into a single FPGA providing the flexibility, performance and time-to-market advantages needed to meet forward error correction standards of 3G wireless basestations. The turbo codes are developed in collaboration with Frontier Design.
"Not only will the new turbo code FPGA solution significantly reduce development time for 3G wireless infrastructure equipment manufacturers, but it will also allow designers to quickly implement incremental improvements and specification changes of forward error correction schemes," said Babak Hedayati, Director of Marketing and Business Development of the IP Solutions Division at Xilinx. "As a result, our customers will have an advantage in the competitive race to implement new wireless standards."
The turbo code LogiCORE products provide a single-chip solution with an optional off-chip memory configuration. The Turbo decoder employs the MAX algorithm and is fully compliant with third generation partnership project (3GPP) specifications (3G TS 25.212 Version 3.3.0). By offering bit error rate (BER) performance of 10-6 for 1,5 dB Eb/No and a 2 Mbps throughput for five decoding iterations, they are ideal for high bandwidth data-oriented applications.
For further information contact Avnet Kopp, (011) 444 2333, [email protected], www.avnetkopp.co.za
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