RF clock fanout buffers
29 September 2010
Telecoms, Datacoms, Wireless, IoT
The ADCLK9xx series is a family of ultrafast clock/data buffers fabricated on Analog Devices’ proprietary complementary bipolar (XFCB-3) silicon-germanium (SiGe) process, which provide a wide choice of fanout capability for flexibility, between one and 12 copies of an input clock, and up to 7,5 GHz toggle rate. They provide ECL/LVPECL outputs with a wideband rms jitter down to 50 fs to 75 fs rms, from a large range of input types such as sine wave, LVPECL, LVDS, CML or CMOS inputs. This family is available in tiny packages from a 3 x 3 mm, 16-lead LFCSP to a 6 x 6 mm, 40-lead LFCSP for the maximum fanout capability.
The ADCLK905/ADCLK907/ADCLK925 can provide 60 fs rms jitter and up to two copies of an input clock with an operation frequency up to 7,5 GHz, while being characterised over an extended temperature range of –40°C to +125°C. The ADCLK944 provides four ECL outputs with 50 fs rms jitter for frequencies up to 7 GHz; the ADCLK946/ADCLK948/ADCLK950/ADCLK954 provide between six and 12 copies of one or two inputs, while yielding a low jitter of 75 fs rms and low output skew of 9 ps typical. The ADCLK914 features high voltage differential signalling (HVDS) operating up to 7,5 GHz with 110 fs rms wideband rms jitter performance suitable for driving the latest high-speed digital-to-analog converters (DACs).
For clocking distribution requiring LVDS or CMOS, Analog Devices also offers the ADCLK8xx series of 1,2 GHz/250 MHz, LVDS/CMOS fanout buffers optimised for low jitter and low power operation, which provide between six and 12 LVDS outputs and up to 24 CMOS outputs. They yield low additive rms wideband jitter from 100 fs for CMOS outputs and from 150 fs for LVDS outputs. The ADCLK8xx series offers power consumption less than 16 mW per channel (100 MHz operation).
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