Programmable logic goes 3D

12 May 2010 Programmable Logic

A privately held, fabless semiconductor startup company called Tier Logic has introduced new 3D-based technology for FPGAs and ASICs, known respectively as TierFPGA and TierASIC devices.

The company’s technology separates user circuits and configuration circuits into three-dimensional stacked layers. By reducing the configuration overhead from the base layers of silicon, Tier Logic claims it can produce smaller, denser, faster, lower-power and more reliable FPGAs. Once the design is stable, the programmable configuration circuitry layer can be replaced by a simple metal layer and turned into an ASIC version. The timing remains identical between the FPGA and ASIC, easing the conversion process.

Although Tier Logic’s 3D structure is different from other FPGAs, it leverages similar architecture and tool flow to existing FPGA providers. New or existing FPGA designs can be synthesised, packed, placed and routed into Tier Logic devices using design tools such as Precision Synthesis from Mentor Graphics, combined with Tier Logic’s Mobius design tool suite. Mobius tools also create the bitstream for TierFPGA devices and the metal-mask data for TierASIC devices.

Like other mainstream FPGAs, TierFPGA devices use SRAM cells to store programming information. However, in the Tier Logic 3D-FPGA structure, these SRAM cells are implemented monolithically in an additional silicon layer built from thin-film transistors (TFTs) that sits on top of the user’s active logic. By pulling these cells out of the active logic layer, the chip area is reduced and the active logic blocks are moved closer together. This smaller, stacked FPGA structure results in lower cost, lower power and higher performance.

By contrast, the ASIC family uses a one-mask hard-wired customer bit pattern for configuration. Thus, all features and resources found in the FPGA are also identically duplicated in the equivalent ASIC. This process allows a single design, once finalised, to be fabricated either as an FPGA or as a timing-exact ASIC with no additional engineering effort, time or cost.

For more information visit www.tierlogic.com

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