Data converter for software radio
17 March 2010
Computer/Embedded Technology
Pentek’s Model 7156 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs from Xilinx and two banks of DDR2 SDRAM. The board uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces. It is also available in PCI, PCIe and cPCI formats.
The front end accepts two full-scale analog HF or IF inputs on front-panel SMC connectors at +8 dBm into 50 Ω with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are well suited for under-sampling applications. The digital outputs are delivered to the FPGA for signal processing, data capture or routing to other module resources.
A TI DAC5688 digital up-converter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the up-convert, interpolate and dual D/A stages. When operating as an up-converter, it interpolates and translates real or complex baseband input signals to any IF centre frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front-panel SMC connectors at +4 dBm into 50 Ω. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2, 4 and 8.
The Model 7156 architecture includes two Virtex-5 FPGAs. The processing FPGA serves as a control and status engine with data and programming interfaces to all of the onboard resources. A second FPGA provides the board’s PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
The board complies with the VITA 42.0 XMC specification for carrier boards. This standard provides for a x4 link with a 3,125 GHz bit clock between the XMC module and the carrier board. With two x4 links, the 7156 achieves 2,5 GBps streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. A front-panel LVPECL clock/sync connector allows multiple modules to be synchronised. In slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In master mode, the LVPECL bus can drive the timing signals for synchronising multiple modules.
For more information contact Rugged Interconnect Technologies, +27 (0)21 975 4524, [email protected], www.ri-tech.co.za
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