Atmel’s SAM9M10 is a high-performance ARM926EJ-based embedded microprocessor (MPU) that integrates a video decoder and 2D acceleration (scaling, rotating, colour space conversion, picture in picture) to provide high-quality video performance in industrial embedded applications.
It is targeted at media rich display and control panels in application segments such as home and commercial buildings, POS (point of sale) terminals, entertainment systems, Internet appliances and medical.
The device includes a 400 MHz MPU that integrates twin parallel external bus interfaces (EBI) to support dual data rate DRAM (DDR2) at 133 MHz. It also integrates high-speed (480 Mbps) USB host and device ports with on-chip transceivers, Ethernet MAC, two interfaces for MMC 4.3 and SDIO/SD Card 2.0, as well as an LCD controller with resistive touch screen support, and CMOS camera and audio interfaces. The SAM9M10 decodes video streams up to D1 (720 x 576 pixels) or WVGA (800 x 480) at 30 frames per second. An evaluation kit is available with free Linux distribution and Microsoft Windows Embedded CE board support packages (BSP).
The SAM9M10 embeds a high-performance hardware video decoder that plays resolutions up to D1 (720x576) or WVGA (800x480) at 30 fps and supports multiple formats: H264, H263, MPEG4, MPEG2, VC1 and JPEG. The LCD display benefits from accelerations, including image scaling and image rotation, colour space conversion (YUV to RGB) for the rendering of compressed formats, and a picture-in-picture capability. The MPU offers integrated power management, slew rate control I/Os with programmable 1,8 or 3,3 V voltage levels, in a 0,8 mm ball pitch package to simplify industrial control design and reduce cost.
The 12-layer system bus matrix is linked to the memory management unit of the processor core, as well as eight central DMA channels, 6 high-speed DMAs, each dedicated to the video decoder, LCD controller, USB host and device, Ethernet MAC, and image sensor interface, 21 Peripheral DMA channels, dual EBI and small blocks of on-chip distributed SRAM to ensure uninterrupted internal and external data flows with minimum processor overhead. The high data speedway architecture enables the SAM9M10 to perform 100 Mpbs+ data transfers, video decoding and user interface rendering in parallel with computationally intensive data processing.
The SAM9M10 contains a number of features that minimise power consumption and reduce the number of external components required. At 400 MHz operation and a 1,0 V core supply, the typical power consumption less than 300 μW/MHz. In backup mode with the RTC running, it only consumes around 8 μA. The system controller incorporates startup, shutdown and power-on reset controllers, on-chip oscillators for 12 MHz and 32 kHz, and a power management controller that fine-tunes power consumption to the required system performance under all conditions of use. I/Os have programmable slew rate to simplify PCB design and support 1,8 and 3,3 V operation to eliminate external level shifters.
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