Xilinx introduced a new generation of its flagship Virtex high-performance field programmable gate array (FPGA) family to enable developers of high-performance, compute-intensive electronic systems to build ‘green’ products under tight design cycles with low development costs.
At up to 50% lower power and 20% lower cost than previous generations, the Virtex-6 family delivers a mix of flexibility, hard intellectual property (IP) cores, transceiver capabilities and development tool support that enables customers to meet the demands of markets with evolving standards and stringent performance requirements in the pursuit of higher bandwidth. With this new generation of Virtex series FPGAs, a broader base of system designers will be able to leverage programmable logic in wireless/wired communications, broadcast, and aerospace and defence applications, among others.
Built on a 40 nm process using third-generation Xilinx ASMBL architecture, the Virtex-6 FPGA family is supported by a new generation of development tools and an extensive library of IP already available for the Virtex-5 FPGA family to ensure productive development and design migration. The new devices operate on a 1,0 V core voltage with a 0,9 V low-power option.
The Virtex-6 family comprises three domain-optimised FPGA platforms that deliver different feature mixes to address a variety of customer applications: The Virtex-6 LXT is optimised for applications that require high-performance logic, DSP and serial connectivity with low-power GTX 6,5 Gbps serial transceivers; Virtex-6 SXT FPGAs are optimised for applications that require ultra high-performance DSP and serial connectivity with low-power GTX 6,5 Gbps serial transceivers; and the Virtex-6 HXT is optimised for communications applications that require the highest-speed serial connectivity with up to 64 GTH serial transceivers supporting up to 11,2 Gbps
For wireless infrastructure applications, the high densities and performance of Virtex-6 FPGAs, coupled with optimised IP developed by Xilinx and its third-party network, enable advanced algorithms such as crest factor reduction (CFR) and digital pre-distortion (DPD), to increase power amplifier efficiency. This makes them suitable for next-generation 3GPP-LTE and LTE advanced base station development.
For wired networking, the Virtex-6 family includes optimised logic ratios, increased performance for wider internal data paths, and multirate transceivers to deliver high overall throughput at low latency. Using these FPGAs, customers can implement an OTU-4 (optical transport unit) framing and enhanced forward error correction (EFEC) solution used in core networks. Optimised logic and transceiver ratios enable developers to implement the 100-Gigabit Ethernet (GE) to OTU-4 framer and critical EFEC using Virtex-6 FPGAs.
As far as broadcast equipment goes, Virtex-6 FPGAs provide a fully programmable, cost-effective solution for meeting current and future broadcast requirements, while enabling differentiation through video quality. High-speed serial transceivers support SD/HD/3G-SDI and embedded audio for all types of broadcast applications. Fully integrated support for 10 Gbps Ethernet enables bridging between broadcast and telecomm networks, allowing fast access and retrieval of stored video content. Increased memory and DSP ratios enable realtime, uncompressed video processing at HD, 2K and 4K resolutions. Optimised logic ratios and power management enable advanced H.264 and JPEG2000 encoding, while reducing power and thermal management requirements for any given performance target.
For aerospace and defence applications, designers are increasingly dependent upon FPGAs for high computational performance and reconfigurable computing in applications ranging from infrastructure communications to electronic warfare and image processing. Virtex-6 SXT FPGAs provide high DSP bandwidth at over 1 TMACS, by combining over 2000 advanced DSP slices with optimised ratios of logic, block RAM and distributed RAM. This computation bandwidth is augmented by over 450 Gbps of serial bandwidth to move data on-chip and off-chip quickly and efficiently.
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