Lattice Semiconductor has released its ispClock5400D family of differential clock distribution ICs, featuring the CleanClock ultra low phase noise PLL. The family currently consists of the six-output 5406D and 10-output 5410D.
The FlexiClock output section of the devices supports multiple logic standards and dual skew control features. The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on the fly via an I²C interface. Design for the devices is supported in the Lattice PAC-Designer software tool.
Typical applications that can benefit from the ispClock5400D devices include supplying high quality reference clocks to high speed serialised communication ICs that use SERDES technology, and the consolidation of components, such as fan-out buffers and zero-delay buffers, typically used for distributing high frequency clocks in a circuit board.
The CleanClock PLL includes an on-chip programmable analog filter and a programmable VCO with input clock frequencies up to 400 MHz. The PAC-Designer software tool automatically determines the parameters of the PLL depending on the input and output clock frequencies. This wideband CleanClock PLL is compatible with the Spreadspectrum clocks required for distributing PCI Express and SATA clocks. The phase noise of the PLL is low enough to be suitable for sourcing clocks to SERDES chips.
The devices provide in-system programmable FlexiClock differential outputs. Each output can be configured to interface with a number of logic standards such as LVDS, MLVDS, HCSL, LVPECL, HSTL and SSTL. The output clock can be individually skewed using the phase angle and time skew mechanisms. In addition, the skew can be changed dynamically in-system through an I²C interface.
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