Agilent Technologies has introduced a comprehensive DDR3 (double data rate 3) protocol debug and validation test suite for digital designers developing computer and embedded memory applications.
Locally sold and supported by Concilium Technologies, the test platform offers a 2,0 GT/s 16962A logic analysis module, a complete probing portfolio for DDR3 BGA (ball grid array) and DIMM (dual in-line memory module) and ensures DDR3 compliance and performance with the software environment.
"The test suite is ideal for R&D engineers integrating a memory controller with the DDR memory devices on the memory subsystem for interoperability testing," according to Steve Alves, managing director of Concilium. "This is a key challenge for most designers as the memory controller design can be developed in-house or acquired from third-party IP (intellectual property)."
The 16962A logic analysis module with 2,0 GT/s state speed and 2 GHz trigger sequence speed enables full capability to reliably trigger and capture DDR3 1600 signals. When used with the new DDR3 probing solution and analysis software tool, this module provides full test capability for system integration in the memory industry.
The W3630A series DDR3 BGA probe provides direct access to the DRAM (dynamic random access memory) with low loading and minimal impact to signal integrity on the embedded system design. The probes are used with oscilloscopes and logic analysers to perform physical layer and functional test.
The N4835A DDR3 slot interposer enables up to 1,6 GT/s high-speed memory bus access through a slot connector in the server and desktop application. The DDR3 slot interposer provides a non-intrusive probing design for quick and easy access to industry-standard DDR3 DIMM.
In addition to announcing a complete DDR solution for the industry, Agilent is introducing its first B4622A DDR2/3 protocol compliance and analysis tool. This tool provides timing and protocol violation checks, an automated physical address trigger setup tool, and overview of system performance through bus statistic information and a histogram view of address access.
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