FPGAs prioritise connectivity and low power
1 April 2009
Programmable Logic
Xilinx has introduced a new generation of its low-cost Spartan field programmable gate array (FPGA) family built for connectivity and low power.
The sixth generation in the Spartan FPGA Series, the Spartan-6 FPGA family is fabricated on a proven, low-power 45 nanometre, nine metal layer, dual-oxide process technology. The family employs an efficient, dual-register 6-input LUT (look-up table) logic structure and a rich selection of built-in system-level blocks including DSP slices, high-speed transceivers, and PCI Express interface cores.
A new high-performance, integrated memory controller core supports DDR, DDR2, DDR3 and mobile DDR memories, along with a hardened multiport bus structure for predictable timing and performance of up to DDR2/DDR3 800 (400 MHz). Design wizards ease the process of building memory controllers for Spartan-6 FPGAs.
The Spartan-6 family comprises two platforms with a mix of features matched to market requirements for price-sensitive, high-volume applications. Spartan-6 LX FPGAs are optimised for applications that prioritise low cost. These devices support up to 150 K logic density, 4,8 Mb memory, integrated memory controllers, and system IP such as DSP blocks, with an open standards-based configuration. Spartan-6 LXT FPGAs expand on this functionality to deliver up to eight 3,125 Gbps GTP transceivers and an integrated PCI Express-compatible core.
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