For decades, quartz crystal oscillators have been problematic in the electronics industry.
Since as early as 1943, reliability has been a main concern with a determination that reliable operation of quartz crystals is only possible when they are sealed in clean, dry, hermetic packages. Although oscillator packages today are smaller, stabilities are tighter and frequencies are higher, quartz crystals are still fabricated in much the same way that they were in 1943. Each new frequency requires a new crystal to be cut, X-rayed, lapped, mounted and sealed into the final package. And so, the quartz industry has remained largely strapped to the same manufacturing methods of the 1940s for producing quartz crystal oscillators.
frequency-programmable architecture for low jitter clock generation
By exploiting advances in fine line CMOS process technology to create a new class of IC-based hybrid oscillator, many of the manufacturing complexities and performance issues traditionally associated with high-frequency resonators can be eliminated. This new class of oscillator combines a fixed low-frequency crystal resonator with a new DSP-based PLL architecture from Silicon Laboratories known as DSPLL. The DSPLL is programmed with a multiplication value to translate the fixed low-frequency crystal frequency to the desired output frequency. Using this architecture, high-frequency clocks operating from 10 MHz to 1,4 GHz have been developed with jitter performance comparable to traditional high-performance voltage-controlled crystal oscillators.
A key advantage of this architecture is that a wide range of low-jitter clock signals can be generated from a conventional fixed frequency quartz crystal. This eliminates the need to fabricate unique HFF crystals or SAW resonators for each frequency. Besides the obvious manufacturing issues associated with maintaining a wide range of different resonator frequencies to support a diverse set of customer requirements, HFF crystals and SAW resonators both have reliability and performance issues that can be significantly improved upon through the new oscillator architecture shown in Figure 1.
A fixed frequency third overtone crystal is used with high-temperature, co-fired ceramic (HTCC) for the package. Industry-standard 7 x 5 mm package dimensions and pad layouts are used for backward compatibility with existing oscillator products.
Revolutionised manufacturing flow
A manufacturing flow that is tailored for short lead times and process optimisation as shown in Figure 3 is made possible by hybrid oscillators incorporating the DSPLL clock synthesis IC. In response to customer orders, 'raw' devices are pulled from inventory, programmed to satisfy customer frequency specifications and shipped. Thus, the order fulfilment flow changes from a complex build-to-order process with eight-week lead times to a simple program-to-order process with one-week lead times.
Improved initial frequency accuracy
Oscillator designs using the DSPLL clock IC for high-resolution frequency synthesis eliminate one of the largest variables determining the initial accuracy of XOs. For HFF VCXOs, initial accuracy may be in the several tens of ppm (parts per million). SAW oscillators are similarly affected by the ability to control ultra-thin film deposition and residual package stresses.
By incorporating high-resolution frequency synthesis into the DSPLL clock IC, the oscillator frequency is set through a simple programming step rather than the traditional two-step tuning process. In contrast, the specifications for the crystal resonator in DSPLL-based hybrid oscillators can be relaxed to an initial accuracy of ±10 000 ppm.
As a result, the fine-tuning step can be eliminated. Because the DSPLL clock IC offers programming resolution of less than one ppb, initial frequency accuracies of one ppm are possible for high frequency XO and VCXO devices.
Improved ageing performance
Achieving adequate pull range is the underlying reason behind the use of HFF crystals for VHF-band VCXOs, such as 155 MHz. Since the oscillator is not directly pulled with the DSPLL architecture, this resonator can readily be used in a VCXO using the Si5301 IC. Since the resonator thickness of a 116,4 MHz third overtone will be four times the thickness of a 155 MHz fundamental, aging performance will be similarly improved. Aging for the module is specified at ±10 ppm over a typical 15-year life. This contrasts with typical SAW or HFF ageing of several ppm/year.
Low jitter clock signals
Jitter is derived from an integration of phase noise over a specified bandwidth. Phase noise for a 1,24 GHz clock signal is shown in Figure 4.
Phase noise performance at offsets lower than 10 kHz is determined primarily by the on-chip crystal oscillator, while the output LVPECL signal levels largely set the noise floor for offset frequencies greater than 10 MHz. Intermediate frequency phase noise performance is determined by the on-chip VCO and associated PLL components. Jitter derived from integration of phase noise is 0,332 ps over the bandwidth of 12 kHz to 20 MHz and 0,319 ps over the bandwidth of 50 kHz to 80 MHz.
Programmable tuning slope
Traditional VCXOs utilise a varactor diode to modify the resonant frequency of the oscillation loop. Non-linear behaviour in the oscillation loop determines the overall tuning slope linearity. The tuning slope, KV, is measured in ppm/V and is directly proportional to the crystal motional capacitance C1. In contrast, the tuning voltage, VC, is digitised on the DSPLL IC through a high-resolution ADC. The resulting digital number is used to slightly modify the frequency synthesis engine and hence the output frequency. Since KV is simply a numerical multiplication factor, differing values of VC can be programmed after the oscillator is assembled. A family of tuning slopes for a 622,08 MHz VCXO is shown in Figure 5.
These results were obtained from a single hybrid oscillator by simply reprogramming the value of KV. Linearity, particularly for the most useful range below 3 V, is dramatically improved compared to conventional varactor-based VCXOs.
Multiple frequency operation from one crystal resonator
Applications are emerging that require multiple clock frequencies slightly offset from each other. Conventional technology VCXOs must use distinct crystals or SAW resonators for each unique frequency. This approach becomes increasingly untenable as the number of required frequencies increases beyond two. Using DSPLL clock synthesis, multiple output frequencies can readily be generated from a single resonator. Dual frequency XO (Si532) and VCXO (Si552) oscillator modules have been developed that provide two selectable output frequencies from a single quartz crystal. In the quad XO (Si534) and VCXO (Si554) series, additional pads are provided on the ceramic package for binary selection of four individual output frequencies. Similar to the dual frequency parts, only one quartz crystal is required, and the choice of output frequencies is arbitrary within the operating bandwidth of the DSPLL IC.
Summary
A new class of crystal oscillators has been developed which offers high resolution, programmable frequency and high performance. These oscillators dramatically simplify the manufacturing process and thereby shorten product lead times. Additional performance advantages include better initial frequency accuracy, long-term ageing and voltage control linearity.
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