The next generation of computer and consumer products will use data serialisation at much higher transmissions speeds. Protection against electrostatic discharge (ESD) is vital for such products. Protection devices must offer compliance with ESD protection standards. Equally important is that protection devices must not compromise the integrity of data transmission.
The new generation of ESD protection devices must provide data transmission transparency through: greater bandwidth; reduced capacitance; and consistent characteristics across production batches. For multiline protection devices it is also vitally important for all line protection circuits to have symmetrical characteristics.
STMicroelectonics offers a broad portfolio of ESD protection devices for many applications. This article spotlights the technical advantages of the DVIULC6-4SC6, a product that offers protection beyond the current standards. At the same time, the DVIULC6-4SC6 ensures unprecedented levels of transparency that ensure digital data transmission integrity.
Why is ESD protection needed?
As shown in Figure 1, an ESD event can easily destroy an IC in several ways, resulting in one or more of these problems:
* Junction leakage.
* Short circuits or burn-out.
* Dielectric rupture.
* Resistor-metal interface rupture.
* Resistor-metal fusing.
Also, soft errors requiring shutdown and restart can be induced by an ESD strike at any time.
These are the reasons why IC suppliers still recommend designing ESD protection devices to protect main chipsets. However, mainly driven by compact design trends, the implementation of external ESD protection poses several challenges such as:
* Highest level of ESD protection in the smallest possible size.
* Negligible effect on high speed digital and analog signal quality.
STMicroelectronics' DVIULC6-4SC6 responds to these requirements.
Diode arrays improve protection
Current line protection uses one diode to suppress ESD events. The diode array clamping concept uses two diodes conducting the positive and negative ESD events to ground. This configuration offers improved protection and highly significant benefits (ultra-low capacitance and high bandwidth) in the transparency of the protection solution during normal operations.
Figure 2 shows a general circuit diagram for a diode array protecting four lines, together with the diode array configuration of the DVIULC6-4SC6 device.
Measured characteristics
Figure 3 shows the test setup used to evaluate the remaining output voltages at the output of the protection device after an ESD event. The test circuit was subjected to the industry standard IEC-61000-4-2 level 4 standard air discharge (Figure 3). The test result in Figure 4 shows that the diode array reduces the perceived discharge from a peak of -15 kV to a peak of 43 V for a negative ESD event. The test result in Figure 5 shows that the diode array reduces the perceived discharge from a peak of +15 kV to a peak of 36 V for a negative ESD event.
The lowest remaining voltage value reduces ESD damage risks, limits energy levels through the core chipset and also avoids any uncontrolled latch up effect. Another advantage offered by a silicon solution is the protection reliability. This solution can withstand multiple ESD events without any shift in electrical characteristics.
The tests show that the diode array topology is one of the best ESD protection solutions that complies with the most severe level of IEC61000-4-2 standard (level 4, 15 kV air discharge and 8 kV contact discharge). The DVIULC6-4SC6 can handle contact and air discharges more severe than those expected in the IEC61000-4-2 standard level 4.
High speed data transparency
In addition to providing in excess of industry standard requirements for ESD protection, there is also the essential requirement that with a protection device there must be negligible impact on the normal performance of the protected application. For high-speed data transparency, this means that the protection device must be optimised for line capacitance and bandwidth. In addition, for multiline protection, the device must present symmetrical characteristics in line capacitance and cut-off frequency to avoid unequalised data channels and crosstalk.
The line capacitance and bandwidth effects on digital data transmission integrity can be evaluated using the common eye diagram technique.
Measured characteristics
The eye diagrams for three different test cases are shown in Figure 6. The fourth eye diagram in Figure 6 is for the test circuit only (generator and test board) without any connected protection device.
The three test cases used to illustrate the importance of transparency are:
* Case 1: DVIULC6-4SC6 - 0,6 pF diode array protection with 5,5 GHz cutoff frequency.
* Case 2: 2,5 pF diode array protection with 2,5 GHz cutoff frequency.
* Case 3: 3,5 pF diode array protection with 800 MHz cutoff frequency.
(Cutoff frequency is that frequency at which the signal strength drops to -3 dB of its base value - see Figure 7.)
The eye diagram results in Figure 6 show that the DVIULC6-4SC6 device (test Case 1) has the least effect on digital data transmission integrity. The eye diagram for test Case 2 shows an increase in the variation of the received signal values (increased variation in the mean values for logical 1 and logical 0, and an increase in rise times and fall times). The eye diagram for test Case 3 shows significant signal degradation; rise times and fall times show significant variation; the bit period value shows significant variation; transition time shows significant variation. Test Cases 2 and 3 indicate risk of data errors at the reception side. The DVIULC6-4SC6 tests (test Case 1) show that risk of data error is minimised.
Transparent effect on rise and fall times
According to the DVI standard (Rev 1.0, 99 April 2nd), minimum rise times and fall times have to be less than 242 ps. Table 1 shows that the DVIULC6-4SC6 solution complies with this standard.
The ultra low capacitance (0,6 pF) of the DVIULC6-4SC6 offers greater margins in designing the board and choosing the semiconductor devices to use. This device's results show extremely low impact on the rise and fall times of the signal (less than 8% variation) and introduction of negligible delays for optimum data transmission signal integrity. With an insertion loss less than -0,2 dB in the 0-1,2 GHz frequency range and a cutoff frequency better than 5,5 GHz, this 0,6 pF diode array protection device is transparent to the application and minimises the introduction of signal distortion and mismatching.
Symmetrical characteristics
Table 2 shows the regular, repeatable values and symmetry of the line capacitance values for the DVIULC-4SC6. In addition to the unprecedented low values, the minimised delta value of line capacitances ensures that data transmission signal integrity is maintained by minimising crosstalk and differential delay values.
Conclusion
The new STMicroelectronics' DVIULC6-4SC6 diode array ESD protection device in SO23-6L package provides the best solution for optimum ESD protection in high speed data transmission applications. In addition, its ultra low capacitance and high bandwidth silicon structure minimises the risk of signal degradation.
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