Clear Logic has announced that it has successfully applied its link-configuration technology to yet another Altera programmable device family. The company claims its new CL3000A family of laser-processed logic devices (LPLD AEs) can be used interchangeably in the same socket as Altera MAX 3000A CPLDs, but cost 30-50% less than Altera devices. As a result, it says, they are ideal for cost-reducing designs originally done using MAX 3000A CPLDs.
CL3000A LPLDs are configured by Clear Logic at the factory, using the customer's MAX 3000A electronic programming file. Clear Logic is offering designers free CL3000A devices configured with MAX 3000A designs. These MAX 3000A programming files can simply be submitted to Clear Logic's website, www.clear-logic.com Within two to three weeks, the company says it will ship configured CL3000A devices that it guarantees will work in the MAX 3000A socket.
Compatible architecture for socket-compatibility
The CL3000A devices have a factory-configurable interconnect array and product term AND array that are similar to and compatible with the logic architecture of MAX 3000A CPLDs. Clear Logic says it accepts MAX 3000A programming files without any modification and guarantees that CL3000A devices function identically in the same socket.
According to Clear Logic, the user-programmability of Altera CPLDs is implemented in transistors in the programmable interconnect array and product term AND array on the device. For example, the EPM3128A uses about 200 000 transistors to achieve its user-programmability. Since Clear Logic's CL3000A LPLDs are not user-programmable, all 200 000 transistors are not required. The result is that there are no transistors in the CL3000A's link-configured interconnect array and there are 80% fewer transistors in the product term AND array. This smaller die size results in a manufacturing cost advantage, claims Clear Logic, allowing it to charge 30-50% less for the CL3000A devices.
The same vertical link technology used to create Clear Logic's CL10K ASICs has been used to develop the CL3000A family. Vertical links require very little silicon area. An added benefit is that they draw no power at all, substantially reducing overall power consumption of CL3000A devices. The vertical link technology also allows very quick turnaround of only two to three weeks from the time Clear Logic receives the MAX 3000A programming file. Production quantities are available within four to six weeks claims the company.
Embedded test circuitry
The architecture of the CL3000A is segmented into small blocks, called TestCells. Each TestCell contains scan registers that can be scanned through the I/O pins when they are activated by a test mode. During extraction of the MAX 3000A programming file, Clear Logic's NoFault AE test vector generation tool automatically generates test vectors, derived from the customer's programming file, that provide 100% stuck-at fault coverage of the device in the customer's configuration. The company says that this level of testability is unavailable with programmable devices.
Clear Logic will offer CL3000A devices with 128 or 256 macrocells. They are available in TQFP packages, with from 100 to 144 pins, and in PQFP packages with 208 pins. The 256 macrocell (5000 gate) CL3256A will be available in the fourth quarter of 2000.
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