New design software reduces FPGA power consumption by up to 35%
25 October 2000
Programmable Logic
Actel has unveiled the R1-2000 release of its Designer Series software. This release contains software enhancements that reduce power consumption of designs implemented in Actel SX-A FPGAs (field programmable gate arrays) by up to 35% without adversely impacting performance. Designer Series R1-2000 also includes a new graphical user interface (GUI) web portal interface and fortified timing and editing tools to speed FPGA design and timing verification. It also includes support for new Actel FPGA families and packages as well as a series of performance enhancements.
"The R1-2000 release of Designer Series software provides our customers with significantly improved features, functionality and benefits," said Jeff Goldberg, Senior Manager of Hardware and Software Marketing at Actel. "It is a major update that improves customer design productivity, while making Actel FPGAs even more attractive for low-power applications."
Extensive analysis of clock network treatment identified potential areas where power consumption could be reduced without impacting design performance. By making routing enhancements to the software, Actel was able to reduce a design's power consumption by up to 35%, making Actel antifuse FPGA devices even more attractive for portable, low-power applications.
Timer, the Designer Series static timing verification and analysis engine, has been enhanced with a back-annotated schematic viewer that displays critical paths in the design. Engineers pushing the performance envelope can see how their critical logic was optimised and implemented in the FPGA. This engine is more flexible and user friendly than previous versions and has been designed to accept even greater functionality in subsequent releases. Using Pin Edit, its enhanced I/O pin attribute editor, engineers can specify I/O attributes for individual signal pins. In addition to specifying I/O characteristics such as slew rate, power-up state and voltage levels, the engineer can specify individual pin capacitance to fine tune line termination, thus minimising transmission line effects prevalent in high-speed designs.
This version of Actel's Designer Series supports file generation for all devices in Actel's SX-A family. Design support has been also been added for next-generation Actel FPGA families targeted for e-Appliance and high-reliability aerospace applications. Designer Series version R1-2000 software now includes support for a new family of 1,0 mm 144, 256 and 484-pin (with 360 I/O) fine-pitch ball grid array packages.
Actel is represented in South Africa by ASIC Design Services
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