Put a fair amount of stress on the bond between printed boards and electronic components and there’s a chance problems will arise, from solder ball cracking to conductor damage to pad cratering.
Although measuring stress is a challenge for EMS and OEM companies, the recently updated joint industry guideline, IPC/JEDEC-9704A ‘Printed Circuit Assembly Strain Gage Test Guideline,’ makes it easier for engineers to run strain gauge tests during the manufacturing process.
“Revision A is about making sure there is a common accepted practice for measuring manufacturing strain on printed board assemblies due to board flexure,” said Jagadeesh Radhakrishnan, a reliability engineer with Intel and leader of the effort within the IPC SMT Attachment Reliability Test Methods Task Group that helped revise the guideline.
Whereas the first-generation document provided industry with target pass/fail points, the A revision, as Radhakrishnan explains, “… changes the focus to providing a methodology. It does not give you targets; it thoroughly explains how to measure strain.”
Revision A includes formulas for calculating strain and describes techniques for analysing data derived from these tests.
The tests can be performed at many stages during the manufacturing of printed board assemblies. Components can be tested during assembly or during test processes in the factory or just before they are packaged.
In addition to the change in focus, IPC/JEDEC-9704A has an expanded scope and provides recommendations for sockets and ceramic capacitors; in the past, it just addressed ball grid arrays (BGAs). “It also changes parameters for in-circuit test fixtures, providing best design practices so users will have fewer issues,” concludes Radhakrishnan.
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A brief synopsis of current global news relating to the electronic engineering fields with regards to company finances, general company news, and engineering technologies.
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