Xilinx announced its 16 nm UltraScale+ family of FPGAs, 3D ICs and MPSoCs, combining new memory, 3D-on-3D and multiprocessing SoC(MPSoC) technologies. The introduction is complemented by a new interconnect optimisation technology known as SmartConnect.
The new FPGA portfolio is made up of Kintex FPGA and Virtex FPGA and 3D IC families, while the new Zynq products include the industry’s first all-programmable MPSoCs. The lineup takes aim at ‘next generation’ applications such as LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS and industrial Internet of Things (IoT).
UltraRAM technology deployed on the new devices attacks one of the largest bottlenecks affecting FPGA and SoC-based system performance and power by enabling SRAM integration. This can be leveraged to create high capacity on-chip memory for a variety of use cases – including deep packet and video buffering – providing predictable latency and performance.
By integrating massive amounts of embedded memory very close to the associated processing engines, designers can achieve greater system performance/Watt and BOM cost reduction. UltraRAM scales up to 432 Mb in a variety of configurations.
The new SmartConnect technology provides additional 20% to 30% performance, area and power advantages through intelligent system-wide interconnect optimisation. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking and logic fabric, SmartConnect applies interconnect topology optimisations to match design-specific throughput and latency requirements while reducing interconnect logic area.
The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and the third generation of Xilinx 3D ICs. Just as FinFETs enable a nonlinear improvement in performance/Watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/Watt over monolithic devices.
The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an extreme level of heterogeneous multiprocessing. They deliver approximately fivefold better system-level performance/Watt relative to previous alternatives. At the centre of the processing subsystem is the 64-bit, quad-core ARM Cortex-A53 processor, capable of hardware virtualisation, asymmetric processing and full ARM TrustZone technology support.
The processing subsystem also includes a dual-core Cortex-R5 processor for real-time deterministic operation, ensuring responsiveness, high throughput and low latency for the highest levels of safety and reliability. A separate security unit enables military-class security solutions such as secure boot, key and vault management, and anti-tamper capabilities – standard requirements for machine-to-machine communication and industrial IoT applications.
For complete graphics acceleration and video compression/decompression, the new devices incorporate an ARM Mali-400 graphics processor as well as an H.265 video codec unit, combined with support for Displayport, MIPI and HDMI. Finally, a dedicated platform and power management unit (PMU) has been added to support system monitoring, system management and dynamic power gating for each of the processing engines.
First tape out and early access release of the design tools are scheduled for the second quarter of 2015, while first ship is scheduled for the fourth quarter.
For more information contact Erich Nast, Avnet Kopp, +27 (0)11 319 8600, [email protected], www.avnet.co.za
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