Texas Instruments has introduced a pair of 4- and 8-output high-speed current steering logic (HCSL) clock fanout buffers that support PCI Express (PCIe) Gen-1, Gen-2 and Gen-3 interface standards.
The LMK00334 creates four buffered copies of an input clock, while the LMK00338 produces eight buffered copies. They deliver low additive jitter (30 fs at 100 MHz (PCIe 3.0) and 86 fs at 156,25 MHz (12 KHz to 20 MHz)) and high supply noise rejection (-75 dBc at 100 MHz), providing system designers with ample jitter margin over the PCIe 3.0 specification.
Both devices are supported in TI’s new WEBENCH Clock Architect to help simplify clock tree design for high-speed communications, networking and data centre systems, including servers, switches and routers. Their two universal inputs operate at up to 400 MHz and offer compatibility with any input type, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL or single-ended clocks and crystal oscillators.
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