Using nanotechnology to cut costs of embedded microchips
3 October 2007
News
Information from Frost & Sullivan Technical Insights
"The microelectronics and IC design industry worldwide has experienced rapid growth in the last four decades, during which transistors have shrunk in size tremendously, resulting in cellphones and computers that are much smaller, lighter, more powerful, and cost less to produce," says NTU's Yeo Kiat Seng, an associate professor in the School of Electrical and Electronic Engineering. "However, transistors are now so small they have reached their physical limitations with power consumption, heat dissipation, and static current leakage becoming major challenges."
The ISNE seeks to overcome those challenges by designing a methodology that is platform independent. It will be directed by Krishna Palem, a professor in computer science at Rice and a visiting professor at NTU.
One design that will be researched is the probabilistic complementary metal oxide semiconductor (PCMOS) developed by Palem's team. PCMOS technology reduces a chip's energy consumption, with the trade-off being increased electronic noise.
For a number of consumer-driven applications, PCMOS will yield good results with lower energy use. For example, Palem experimented with running cellphone-style streaming video applications, comparing PCMOS chips (which used five times less power) with traditional cellphone chips. There was no appreciable difference in picture quality. The research team is designing and building the first production prototype of PCMOS chips.
Notes Palem, "A major goal of the collaboration is to help sustain Moore's Law and exploit the exponential rate at which electronic components have been shrinking for more than four decades."
ISNE will be based at NTU in Singapore.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, patrick.cairns@frost.com
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