Finer lines for next generation microchips

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20 August 2008 News

Information from Frost & Sullivan Technical Insights

The ability to draw finer lithographic patterns determines the semiconductor industry's ability to move into lower process nodes. While the 65 nm feature size is the minimum feature size in current day processors, leading semiconductor firms seem to be poised to plunge into the 32 nm node very soon and are confident of achieving 25 nm within five years.

There are numerous research initiatives that contribute to the industry's growth in this direction. One such effort is that of a research group at Massachusetts Institute of Technology (MIT). The group has developed a high-precision variant of a technique called interference lithography that enables the generation of finer patterns of lines over large areas with the support of a tool called a nanoruler.

The technique is expected to impact on the next generation of computer memory and integrated circuits, as well as advanced solar cells and other devices. With advanced techniques the team has been able to create patterns of width 25 nm with interline spacing of 25 nm.

Interference lithography is a technique where two beams of light interfere with each other to produce interference fringes. These fringes are subsequently recorded in the surface as lines and spaces, using the same techniques common to the patterning of miniscule designs on computer chips.

The high-precision variant of this technique referred to as scanning beam interference lithography (SBIL), uses 100 MHz sound waves, controlled by custom high-speed electronics, to diffract and frequency-shift the laser light. This results in rapid patterning of large areas with unprecedented control over feature geometry.

The SBIL technique has apparently improved the capabilities of interference lithography by enabling precise repeatable pattern registration and overlay over large areas. The high-precision phase detection algorithm and image reversal process developed by the MIT researchers is said to have supported the development of this technique substantially.

According to the team, it is only material issues such as line sidewall roughness that are restraining the growth of the technology to much finer scales. With a lot of solutions steadily emerging to address these issues, the team feels that a progress further in this direction may be relatively easy.

For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, patrick.cairns@frost.com, www.frost.com

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Finer lines for next generation microchips

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